This disclosure relates to chemical mechanical planarization (CMP) of semiconductor wafers and more particularly, to CMP (polishing) compositions and methods for removing barrier materials of semiconductor wafers in the presence of underlying dielectric layers with reduced erosion of the dielectric layer.
The semiconductor industry relies upon metal interconnect metals in forming integrated circuits on semiconductor wafers. These interconnect metals, such as aluminum, copper, gold, nickel, and platinum group metals, silver, tungsten and their alloys have a low electrical resistivity. Copper metal interconnects provide excellent conductivity at a low cost. Because copper is highly soluble in many dielectric materials, such as silicon dioxide or doped versions of silicon dioxide, integrated circuit fabricators typically apply a diffusion barrier layer to prevent the copper diffusion into the dielectric layer. For example, barrier layers for protecting dielectrics include, tantalum, tantalum nitride, tantalum-silicon nitrides, titanium, titanium nitrides, titanium-silicon nitrides, titanium-titanium nitrides, titanium-tungsten, tungsten, tungsten nitrides and tungsten-silicon nitrides.
Chip manufacturing uses CMP processes to planarize semiconductor substrates after the deposition of the metal interconnect layers. Typically, the polishing process uses a “first-step” slurry specifically designed to rapidly remove the metal interconnect. Then the CMP process includes a “second-step” slurry to remove the barrier layer. Typically, the second-step slurries selectively remove the barrier layer without adversely impacting the physical structure or electrical properties of the interconnect structure. In addition to this, the second step slurry should also possess low erosion rates for dielectrics. Erosion refers to unwanted recesses in the surface of dielectric layers that results from removing some of the dielectric layer during the CMP process. Erosion that occurs adjacent to the metal in trenches causes dimensional defects in the circuit interconnects. These defects contribute to attenuation of electrical signals transmitted by the circuit interconnects and impair subsequent fabrication. The removal rate of the barrier versus the removal rate of the metal interconnect or the dielectric layer is known as the selectivity ratio. For purposes of this specification removal rate refers to a removal rate as change of thickness per unit time, such as, Angstroms per minute.
Typical barrier removal CMP compositions require a high abrasive concentration, such as at least 7.5 weight percent, in a fluid CMP composition to remove a barrier material. These high-abrasive slurries, however, tend to result in unacceptable dielectric erosion rates. In addition to this, high abrasive concentrations can result in peeling or delaminating of low-k dielectric layers from semiconductor wafers. Furthermore, the peeling or delaminating of low-k dielectrics becomes a greater problem at pressures of 21.7 kPa (3 psi) and above.
EP1150341 to Uchida et al. teaches a CMP composition for use in CMP processes, comprising an oxidizing agent, an oxidized metal etchant, abrasives, a protective film-forming agent, which comprises a carboxylic acid polymer and a dissolution promotor. This composition is designed for first-step copper removal; and it does not effectively remove a barrier layer while reducing erosion.
There remains an unsatisfied demand for aqueous CMP compositions that can selectively remove tantalum barrier layers while simultaneously reducing erosion of dielectric materials. In addition there is a demand for a CMP composition that removes barrier layers from patterned wafers with decreased defectivity rates.